Computer Science and Engineering

• Best paper award
• Best paper award
• Industrial Fellow (Honorary)
• Senior Member IEEE
• Royal Society International Incoming Short Visits

Journal
• Energy-Aware Service Allocation: A Crow Search-Based Approach Ray Chowdhury C., Misra S., Mandal C. By IEEE Transactions on Green Communications and Networking 7 211-223 (2023)
• SeamFlow: Seamless Flow Forwarding in Energy Harvesting-Enabled Access Points of SDWLAN Chowdhury C.R., Misra S., Mandal C., Bera S. By IEEE Transactions on Sustainable Computing 8 94-108 (2023)
• SCOPE: Cost-Efficient QoS-Aware Switch and Controller Placement in Hybrid SDN Maity I., Misra S., Mandal C. By IEEE Systems Journal 16 4873-4880 (2022)
• Translation validation of coloured Petri net models of programs on integers Bandyopadhyay S., Sarkar D., Mandal C., Giese H. By Acta Informatica - (2022)
• ETHoS: Energy-Aware Traffic Engineering for Sustainable Hybrid SDN Maity I., Misra S., Mandal C. By IEEE Transactions on Sustainable Computing - (2022)
• Distinct pathoclinical clusters among patients with uncontrolled type 2 diabetes: results from a prospective study in rural India Aravindakshan M.R., Maity S.K., Paul A., Chakrabarti P., Mandal C., Sarkar J. By BMJ Open Diabetes Research and Care 10 - (2022)
• Clustering Based Parameter Estimation of Thyroid Hormone Pathway Ghosh D., Mandal C. By IEEE/ACM Transactions on Computational Biology and Bioinformatics 19 343-354 (2022)
• Sustainable Maintenance of Connected Dominating Set by Solar Energy Harvesting for IoT Networks Chowdhury C.R., Mandal C., Misra S. By IEEE Transactions on Green Communications and Networking 6 2115-2127 (2022)
• CORE: Prediction-Based Control Plane Load Reduction in Software-Defined IoT Networks Maity I., Misra S., Mandal C. By IEEE Transactions on Communications 69 1835-1844 (2021)
• IEEE 802.11k-based Lightweight, Distributed and Cooperative Access Point Coverage Estimation Scheme in IoT Networks Chowdhury C.R., Misra S., Mandal C. By IEEE Internet of Things Journal - (2021)
• DART: Data Plane Load Reduction for Traffic Flow Migration in SDN Maity I., Misra S., Mandal C. By IEEE Transactions on Communications 69 1765-1774 (2021)
• Automatic Generation of Route Control Chart from Validated Signal Interlocking Plan Das A., Gangwar M.K., Ghosh D., Mandal C., Sengupta A., Waris M.M. By IEEE Transactions on Intelligent Transportation Systems 22 6516-6525 (2021)
• Secure Path Balanced BDD-Based Pre-Charge Logic for Masking De P., Parampalli U., Mandal C. By IEEE Transactions on Circuits and Systems I: Regular Papers 67 4747-4760 (2020)
• Verification of parallelising transformations of KPN models Karfa C., Sarkar D., Mandal C. By IET Cyber-Physical Systems: Theory and Applications 4 276-289 (2019)
• Tensor-Based Rule-Space Management System in SDN Maity I., Mondal A. , Misra S. , Mandal C. By IEEE Systems Journal 13 3921-3928 (2019)
• Equivalence checking of Petri net models of programs using static and dynamic cut-points Bandyopadhyay S., Sarkar D., Mandal C. By Acta Informatica 56 321-383 (2019)
• Path-balanced logic design to realize block ciphers resistant to power and timing attacks De P., Mandal C., Prampalli U. By IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 1080-1092 (2019)
• CURE: Consistent Update with Redundancy Reduction in SDN Maity I., Mondal A. , Misra S. , Mandal C. By IEEE Transactions on Communications 66 3974-3981 (2018)
• Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs Ghoshal B., Mandal C. , Sengupta I. By Integration: The VLSI Journal 59 168-178 (2017)
• Deriving Bisimulation Relations from Path Based Equivalence Checkers Banerjee K., Sarkar D. , Mandal C. By Formal Aspects of Computing 29 365-379 (2017)
• Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers Banerjee K., Sarkar D. , Mandal C. By IEEE Transactions on Software Engineering 43 - (2017)
• A virtual laboratory for basic electronics, Dhang S., Mandal C. By Journal of Engineering, Science and Management Education 10 67-74 (2017)
• Distributed Construction of Minimum Connected Dominating Set in Wireless Sensor Network Using Two-Hop Information Mohanty J. P., Mandal C. , Reade C. M. By Computer Networks 123 137-152 (2017)
• COLDVL: A Virtual Laboratory Tool with Novel Features to Support Learning in Logic Design and Computer Organisation Roy G., Ghosh D. , Mandal C. By Journal of Computers in Education 4 461-490 (2017)
• Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers Banerjee K., Sarkar D. , Mandal C. By IEEE TSE PrePrint - (2016)
• A Path Construction Algorithm for Translation Validation using PRES+ Models Bandyopadhyay S., Sarkar D. , Mandal C. , Banerjee K. , Duddu K. R. By Parallel Processing Letters 26 1-15 (2016)
• Construction of Minimum Connected Dominating Set in Wireless Sensor Networks Using Pseudo Dominating Set Mohanty J. P., Mandal C. , Reade C. M., Das A. By Ad Hoc Networks 42 61-73 (2016)
• Verification of Code Motion Techniques using Value Propagation Banerjee K., Karfa C. , Sarkar D. , Mandal C. By IEEE Transactions on CAD 33 1180-1193 (2014)
• Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs Banerjee K., Sarkar D. , Mandal C. By IEEE Transactions on CAD 33 2016-2019 (2014)
• Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviours Karfa C., Banerjee K. , Sarkar D. , Mandal C. By IEEE Transactions on CAD 32 1787-1800 (2013)
• Formal Verification of Code Motion Techniques using Data-flow Driven Equivalence Checking Karfa C., Mandal C. , Sarkar D. By ACM TODAES 17 3001-3037 (2012)
• POWER-SIM : An SOC Simulator for Estimating Power Profiles of Mobile Workloads Ghosh P., Hazra A. , Gonnabhaktula R. , Bhilegaonkar N. , Dasgupta P. , Mandal C. , Paul K. By Journal of Low-Power Electronics (JOLPE) 8 293-303 (2012)
• A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies Pandit S., Mandal C. , Patra A. By VLSI Design 1-17 (2011)
• Minimum Connected Dominating Set using a Collaborative Cover Heuristic for Adhoc Sensor Networks Misra R., Mandal C. By IEEE Transactions on Parallel and Distributed Systems 21 292-302 (2010)
• An Automated High-Level Topology Generation Procedure for Continuous-Time Modulator Pandit S., Mandal C. , Patra A. By Integration, the VLSI Journal 43 289-304 (2010)
• Verification of Datapath and Controller Generation Phase in High-level Synthesis of Digital Circuits Karfa C., Sarkar D. , Mandal C. By IEEE Transactions on CAD 29 479-492 (2010)
• Efficient Clusterhead Rotation via Domatic Partition in Self-Organizing Sensor Networks Misra R., Mandal C. By Wireless Communications and Mobile Computing 9 1040-1058 (2009)
• Rotation of CDS via Connected Domatic Partition in Ad hoc Sensor Networks Misra R., Mandal C. By IEEE Transactions on Mobile Computing 6 488-499 (2009)
• A Fast Exploration Procedure for Analog High-Level Specification Translation Pandit S., Bhattacharya S. K., Mandal C. , Patra A. By IEEE Transactions on CAD 27 1493-1497 (2008)
• An Equivalence Checking Method for Scheduling Verification in High-level Synthesis Karfa C., Sarkar D. , Mandal C. , Kumar P. By IEEE Transactions on CAD 27 556-569 (2008)
• A System for Automatic Evaluation of `C' Programs - features and interfaces Mandal A., Mandal C. , Reade C. By International Journal of Web-Based Learning and Teaching Technologies (IJWLTT) 2 24-39 (2007)
• Genetic Algorithms for High-Level Synthesis in VLSI Design Mandal C., Chakrabarti P. P. By Materials and Manufacturing Processes 18 355-383 (2003)
Innovation: Project
• ERP services for Indian Institute for Petroleum Engineering Mandal C. By - (2022)
• Signalling system for Indian Railways Mandal C. By - (2022)
• SMILE ERP for NITs Mandal C. By - (2021)
Educational Package
• Web Based Course Management Mandal C. By - (2020)
• Virtual laboratory on Basic Electronics Mandal C. By - (2017)
• Virtual laboratory for Computer Organisation and Architecture Mandal C. By - (2014)
Conferences
• Traffic-Aware Consistent Flow Migration in SDN Maity I., Misra S. , Mandal C. By Proceedings of IEEE ICC 2020 1-6 (2020)
• Traffic-Aware Consistent Flow Migration in SDN Maity I., Misra S., Mandal C. By IEEE International Conference on Communications 2020-June - (2020)
• Samatulyataone: A path based equivalence checker Bandyopadhyay S., Sarkar D., Mandal C. By ACM International Conference Proceeding Series - (2019)
• An Equivalence Checking Framework for Array-Intensive Programs Banerjee K., Mandal C. , Sarkar D. By - (2017)
• Formal Verification of Movement Authorities in Automatic Train Control Systems Ghosh S., Dasgupta P. , Mandal C. , Katiyar A. By IET International Conference on Railway Engineering - (2016)
• Workload Driven Power Domain Partitioning Dobriyal A., Gonnabattula R. , Dasgupta P. , Mandal C. By VLSI Design and Test (VDAT) 147-155 (2012)
• POWER-SIM : An SOC Simulator for Estimating Power Profiles of Mobile Workloads Ghosh P., Hazra A. , Gonnabhaktula R. , Bhilegaonkar N. , Dasgupta P. , Mandal C. , Paul K. By International Symposium on Electronic System Design (ISED) 273-278 (2011)
• Formal Verification Coverage: Are the RTL Properties Covering the Design's Architectural Intent? Basu P., Das S. , Dasgupta P. , Chakrabarti P. P., Mandal C. , Fix L. By DATE 2004 - (2004)
Book Chapter/Section
• Connected Dominating Set in Wireless Sensor Network Mohanty J. P., Mandal C. By Handbook of Research on Advanced Wireless Sensor Network Applications, Protocols, and Architectures - (2016)
• A Survey of CDS Construction Techniques for Ad hoc Sensor Networks Das A., Mandal C. , Reade C. M. By Wireless Sensor Networks From Theory to Applications 247-264 (2013)
Book
• Nano-scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design Pandit S., Mandal C. , Patra A. By - (2013)
• Verification and Synthesis of Digital Circuits: High-level Synthesis and Equivalence Checking Karfa C., Sarkar D. , Mandal C. By - (2010)

Principal Investigator

• Lan Driver Development on HP-UX Platform
• DESIGN OF A PROCESSOR HAVING AN ASYNCHRONOUS ALU TO COUNTER SIDE CHANNEL (POWER)
• EXTENDING THE SCOPE OF EQUIVALENCE CHECKING IN COMPLEX EMBEDDED SYSTEM DESIGN VERIFICATION
• VIRTUAL LAB FOR COMPUTER ORGANIZATION AND ARCHITECTURE
• Integrated high-level synthesis to satisfy protocol and data processing specifications
• Modelling and validation of interlocking for railway signalling systems
• Train Collision Avoidance System [TCAS] Phase II Project for having Features Similar to European Train Control System [ETCS] Level 2 for Higher Speeds
• Incorporating Cab-signalling into Interlocked Signalling Design with Verification (IMPRINT-2)

Co-Principal Investigator

• Design and development of multi-material deposition (MMD) system
• PLATFORM ARCHITECTURE MODELING FOR EXPLORING POWER MANAGEMENT STRATEGIES
• SPECIAL MANPOWER DEVELOPMENT PROGRAMME FOR VLSI DESIGN AND RELATED SOFTWARE (SMDP-II)