Indian Institute of Technology Kharagpur |

Journal

Improved Mapping of Quantum Circuits to IBM QX Architectures Kolay A., Hillmich S. , Datta K. , Wille R. , Sengupta I. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - (Accepted/In-Press)
FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications Yadav D. N., Thangkhiew P. L., Datta K. , Chakraborty S. , Drechsler R. , Sengupta I. By Journal of Electronic Testing - (Accepted/In-Press)
Sorting of Fully Homomorphic Encrypted Cloud Data: Can Partitioning be effective? Chatterjee A., Sengupta I. By IEEE Transactions on Services Computing - (Accepted/In-Press)
In-Memory Computing on Resistive RAM Systems Using Majority Operation Lalchhandama F., Sahani M., Srinivas V.M., Sengupta I., Datta K. By Journal of Circuits, Systems and Computers 31 - (2022)
A lightweight device-level Public Key Infrastructure with DRAM based Physical Unclonable Function (PUF) for secure cyber physical systems Chanda S., Luhach A.K., Alnumay W., Sengupta I., Sinha Roy D. By Computer Communications 190 87-98 (2022)
CoMIC: Complementary Memristor based In-memory Computing in 3D Architecture Fanchun L., Datta K. , Chakraborty S. , Dresler R. , Sengupta I. By Journal of Systems Architecture 126 - (2022)
Feed-Forward learning algorithm for resistive memories Yadav D.N., Thangkhiew P.L., Datta K., Chakraborty S., Drechsler R., Sengupta I. By Journal of Systems Architecture 131 - (2022)
Conformance Testing for Finite State Machines Guided by Deep Neural Network Rahaman H., Chattopadhyay S., Sengupta I. By Journal of Circuits, Systems and Computers - (2022)
Sorting of Fully Homomorphic Encrypted Cloud Data: Can Partitioning be effective? Chatterjee A., Sengupta I. By IEEE Transactions on Services Computing 13 545-558 (2020)
An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD) Thangkhiew P. L., Zulehner A. , Wille R. , Datta K. , Sengupta I. By Integration, The VLSI Journal 71 125-133 (2020)
An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD) Thangkhiew P.L., Zulehner A., Wille R., Datta K., Sengupta I. By Integration 71 125-133 (2020)
Scheduling algorithms for reservoir- and mixer-aware sample preparation with microfluidic biochips Agarwal V., Singla A. , Samiuddin M. , Roy S. , Ho T. , Sengupta I. , Bhattacharyya B. By Integration 65 428-443 (2019)
Scheduling algorithms for reservoir- and mixer-aware sample preparation with microfluidic biochips Agarwal V., Singla A., Samiuddin M., Roy S., Ho T.-Y., Sengupta I., Bhattacharya B.B. By Integration 65 428-443 (2019)
Improved Mapping of Quantum Circuits to IBM QX Architectures Kole A., Hillmich S., Datta K., Wille R., Sengupta I. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - (2019)
Thermal-aware test scheduling strategy for network-on-chip based systems Manna K., Sagar C. , Chattopadhyay S. , Sengupta I. By ACM Journal on Emerging Technologies in Computing (JETC) 15 6.1-6.27 (2019)
A Scalable In-Memory Logic Synthesis Approach Using Memristor Crossbar Gharpinde R., Thangkhiew P. L., Datta K. , Sengupta I. By IEEE Transactions on VLSI Systems 26 355-388 (2018)
Thermal-aware Application Mapping Strategy for Network-on-Chip based System Design Manna K., Mukherjee P. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on Computers 67 528-542 (2018)
Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design Manna K., Mukherjee P. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on Computers 67 528-542 (2018)
A New Heuristic for N-Dimensional Nearest Neighbor Realization of a Quantum Circuit Kole A., Datta K. , Sengupta I. By IEEE Transactions on CAD of Integrated Circuits and Systems 37 182-192 (2018)
Translating Algorithms to Handle Fully Homomorphic Encrypted Data on the Cloud Chatterjee A., Sengupta I. By IEEE Transactions on Cloud Computing 6 287-300 (2018)
Translating Algorithms to Handle Fully Homomorphic Encrypted Data on the Cloud Chatterjee A., Sengupta I. By IEEE Transactions on Cloud Computing 287-300 (2018)
Scheduling algorithms for reservoir- and mixer-aware sample preparation with microfluidic biochips Agarwal V., Singla A. , Samiuddin M. , Roy S. , Ho T. , Sengupta I. , Bhattacharya B. B. By Integration: The VLSI Journal - (2018)
Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs Ghoshal B., Mandal C. , Sengupta I. By Integration: The VLSI Journal 59 168-178 (2017)
A New Object Searching Protocol for Multi-tag RFID Dhal S., Sengupta I. By Wireless Personal Communications 97 3547-3568 (2017)
Small test set generation with high diagnosability Bhar A., Chattopadhyay S. , Sengupta I. , Kapur R. By Journal of Circuits, Systems, and Computers 25 1-18 (2016)
Small Test Set Generation with High Diagnosability Bhar A., Chattopadhyay S. , Sengupta I. , Kapur R. By Journal of Circuits, Systems and Computers 25 - (2016)
In-field test for permanent faults in FIFO buffers of NoC routers Ghoshal B., Manna K. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on VLSI Systems 24 393-397 (2016)
In-field test for permanent faults in FIFO buffers of NoC routers B Ghoshal, K Manna, S Chattopadhyay Ghosal B., Manna K. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on Very Large Scale Integration 24 393-397 (2016)
Integrated Through Silicon Via Placement and Application Mapping for 3D Mesh Based NoC Design Manna K., Swamy S. , Chattopadhyay S. , Sengupta I. By ACM Transactions on Embedded Computing Systems (TECS) 16 - (2016)
Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design Manna K., Swamy S. , Chattopadhyay S. , Sengupta I. By ACM Transactions on Embedded Computing Systems 16 24- (2016)
A heuristic for linear nearest neighbor realization of quantum circuits by SWAP gate insertion using N-gate lookahead Kole A., Datta K. , Sengupta I. By IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 62-72 (2016)
A post-synthesis optimization technique for reversible circuits exploiting negative control lines Datta K., Sengupta I. , Rahaman H. By IEEE Transactions on Computers 64 1208-1214 (2015)
Performance modelling and acceleration of binary Edwards curve processor on FPGAs Chatterjee A., Sengupta I. By International Journal of Electronics and Information Engineering 80-93 (2015)
Thermal-aware multifrequency network-on-chip testing using particle swarm optimisation Manna K., Veeramreddy C. R., Chattopadhyay S. , Sengupta I. By International Journal of High Performance Systems Architecture 5 141-152 (2015)
All optical design of binary adders using semiconductor optical amplifier assisted Mach-Zehnder interferometer Datta K., Chattopadhyay T. , Sengupta I. By Microelectronics Journal 46 839-847 (2015)
Scan chain masking for diagnosis of multiple chain failures in a space compaction environment Kundu S., Chattopadhyay S. , Sengupta I. , Kapur R. By IEEE Transactions on VLSI Systems 23 1185-1195 (2015)
Scan chain masking for diagnosis of multiple chain failures in a space compaction environment Kundu S., Chattopadhyay S. , Sengupta I. , Kapur R. By IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 - (2015)
Construction of RSBFs with improved cryptographic properties to resist differential fault attack on grain family of stream ciphers Mazumdar B., Mukhopadhyay D. , Sengupta I. By Cryptography and Communications 7 35-69 (2015)
Construction of RSBFs with improved cryptographic properties to resist differential fault attack on grain family of stream ciphers Mazumdar B., Mukhopadhyay D. , Sengupta I. By Cryptography and Communications 7 35-69 (2015)
An approach to reversible logic synthesis using input and output permutations Datta K., Sengupta I. , Rahaman H. , Drechsler R. By Transactions on Computational Science 24 92-110 (2014)
Framework for multiple-fault diagnosis based on multiple fault simulation using particle swarm optimization Kundu S., Jha A. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 696-700 (2014)
Framework for multiple-fault diagnosis based on multiple fault simulation using particle swarm optimization Kundu S., Jha A. , Chattopadhyay S. , Sengupta I. , Kapur R. By IEEE Transactions on VLSI Systems 22 696-700 (2014)
An improved reversible circuit synthesis approach using clustering of ESOP cubes Datta K., Rathi G. , Sengupta I. , Rahaman H. By ACM Journal on Emerging Technologies in Computing (JETC) 11 1-16 (2014)
Constrained Search for a Class of Good Bijective S-Boxes With Improved DPA Resistivity Mazumdar B., Mukhopadhyay D. , Sengupta I. By IEEE Transactions on Information Forensics and Security 8 2154-2163 (2013)
A metric for test set characterization and customization toward fault diagnosis Kundu S., Pal S. , Chattopadhyay S. , Sengupta I. By IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - (2013)
Particle swarm optimization based reversible circuit synthesis using mixed control Toffoli gates Datta K., Sengupta I. , Rahaman H. By Jounal of Low Power Electronics 9 363-372 (2013)
An efficient routing technique for mesh-of-tree-based NoC and its performance comparison Manna K., Chattopadhyay S. , Sengupta I. By International Journal of High Performance Systems Architecture 4 25-37 (2012)
Design of a high performance Binary Edwards Curve based processor secured against side channel analysis. Chatterjee A., Sengupta I. By Integration VLSI 331-340 (2012)
Effect of glitches against masked AES S-box implementation and countermeasure Alam M., Ghosh S. , M.j. Mohan M. , Mukhopadhyay D. , Chowdhury D. R., Sengupta I. By IET Information Security 3 34-44 (2009)
Two New Algorithms for Static Virtual Topology design in Optical WDM Networks Datta R., Ghose S. , Sengupta I. By International Journal on Wireless and Optical Communications 4 1-14 (2007)
Static and Dynamic Connection Establishment in WDM Optical Networks: A Review Datta R., Sengupta I. By IETE Journal of Research 51 209-222 (2005)
New Schemes for Connection Establishment in GMPLS Environment for WDM Networks Datta R., Turuk A. K., Ghose S. , Kumar R. , Sengupta I. By International Journal on Wireless and Optical Communications 2 83-98 (2004)
An Algorithm for Optimal assignment of a wavelength in a Tree Topology and its Application in WDM networks Datta R., Mitra B. , Ghose S. , Sengupta I. By IEEE Journal on Selected Areas in Communication (JSAC) 22 1589-1600 (2004)
An Algorithm for Optimal Assignment of a Wavelength in a Tree Topology and Its Application in WDM Networks Datta R., Mitra B. , Ghose S. , Sengupta I. By IEEE Journal on Selected Areas in Communications 22 - (2004)
Theory and application of non-group cellular automata for message authentication Dasgupta P., Chattopadhyay S. , Sengupta I. By Journal of Systems Architecture 47 383-404 (2001)
Cellular automata-based recursive pseudoexhaustive test pattern generator Dasgupta P., Chattopadhyay S. , Chaudhuri P. P., Sengupta I. By IEEE Transactions on Computers 50 177-185 (2001)

Conferences

Mapping Quantum Circuits to 2-Dimensional Quantum Architectures Datta K., Kole A., Sengupta I., Drechsler R. By Lecture Notes in Informatics (LNI), Proceedings - Series of the Gesellschaft fur Informatik (GI) P-326 1109-1120 (2022)
Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking Rahaman H., Chattopadhyay S., Sengupta I., Das D.K., Bhattacharya B.B. By Proceedings - 2022 35th International Conference on VLSI Design, VLSID 2022 - held concurrently with 2022 21st International Conference on Embedded Systems, ES 2022 246-251 (2022)
Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture Datta K., Kole A., Sengupta I., Drechsler R. By Proceedings of The International Symposium on Multiple-Valued Logic 2022-May 35-42 (2022)
Transfer Fault Detection in Finite State Machines Using Deep Neural Networks Rahaman H., Chattopadhyay S., Sengupta I. By Lecture Notes in Electrical Engineering 811 139-152 (2022)
Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications Datta K., Froehlich S., Shirinzadeh S., Yadav D.N., Sengupta I., Drechsler R. By IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2022-October - (2022)
An Improved Test Pattern Reordering Framework Targeting Test Power Reduction Maity H., Chattopadhyay S., Sengupta I., Bhattacharya P., Patankar G. By 2021 IEEE International Test Conference India, ITC India 2021 - (2021)
A Deep Neural Network Guided Testing Approach for Finite State Machines Rahaman H., Chattopadhyay S., Sengupta I. By 4th International Symposium on Devices, Circuits and Systems, ISDCS 2021 - Conference Proceedings - (2021)
Efficient Construction of Functional Representations for Quantum Algorithms Burgholzer L., Raymond R., Sengupta I., Wille R. By Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 12805 LNCS 227-241 (2021)
Analyzing fault tolerance behaviour in memristor-based crossbar for neuromorphic applications Yadav D.N., Datta K., Sengupta I. By 2020 IEEE International Test Conference India, ITC India 2020 - (2020)
Analyzing Fault Tolerance Behaviour in Memristor-based Crossbar for Neuromorphic Applications Yadav D. N., Datta K. , Sengupta I. By International Test Conference India 2020 1-9 (2020)
A New Test Vector Reordering Technique for Low Power Combinational Circuit Testing Maity H., Khatua K., Chattopadhyay S., Sengupta I., Patankar G., Bhattacharya P. By 3rd International Symposium on Devices, Circuits and Systems, ISDCS 2020 - Proceedings - (2020)
Resource optimal realization of fault-tolerant quantum circuit Kole A., Sengupta I. By 2020 IEEE International Test Conference India, ITC India 2020 - (2020)
Resource Optimal Realization of Fault-Tolerant Quantum Circuit Kole A., Sengupta I. By International Test Conference India 2020 1-10 (2020)
Mapping of boolean logic functions onto 3D memristor crossbar Naveen Murali G., Satya Vardhan P., Lalchhandama F., Datta K., Sengupta I. By Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019 500-501 (2019)
Exploiting negative control lines and nearest neighbor for improved comparator design Bose T., Datta K., Sengupta I. By Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019 514-515 (2019)
Design and implementation of threshold logic functions using memristors Danaboina Y.K.Y., Samanta P., Datta K., Chakrabarti I., Sengupta I. By Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019 518-519 (2019)
Fault coverage enhancement via weighted random pattern generation in BIST using a DNN-driven-pso approach Maity H., Khatua K., Chattopadhyay S., Sengupta I., Patankar G., Bhattacharya P. By Proceedings - 2019 International Conference on Information Technology, ICIT 2019 228-233 (2019)
A staircase structure for scalable and efficient synthesis of memristor-aided logic Zulehner A., Datta K., Sengupta I., Wille R. By Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 237-242 (2019)
A staircase structure for scalable and efficient synthesis of memristor-aided logic Zulehner A., Datta K. , Sengupta I. , Wille R. By 24th Asia and South Pacific Design Automation Conference (ASP-DAC) 237-242 (2019)
Modelling and Simulation of Non-Ideal MAGIC NOR Gates on Memristor Crossbar Murali N., Lalchhandama F., Datta K., Sengupta I. By Proceedings of the 2018 8th International Symposium on Embedded Computing and System Design, ISED 2018 124-128 (2018)
Test pattern generation effort evaluation of reversible circuits Kole A., Wille R. , Datta K. , Sengupta I. By 9th Conference on Reversible Computation - (2017)
Design of efficient quantum circuits using nearest neighbor constraint in 2D architecture Marbaniang L., Kole A. , Datta K. , Sengupta I. By 9th Conference on Reversible Computation - (2017)
Improved decomposition of multiple-control ternary Toffoli gates using Muthukrishnan-Stroud quantum gates Rani P. N., Kole A. , Datta K. , Sengupta I. By 9th Conference on Reversible Computation - (2017)
A nearest neighbor quantum cost metric for the reversible circuit level Kole A., Datta K. , Wille R. , Sengupta I. By IEEE Region 10 Conference (TENCON) 2943-2948 (2017)
A New Logic Encryption Strategy Ensuring Key Interdependency Karmakar R., Prasad N. , Chattopadhyay S. , Kapur R. , Sengupta I. By VLSI Design 2017 429-434 (2017)
A New Logic Encryption Strategy Ensuring Key Interdependency Karmakar R., Prasad N. , Chattopadhyay S. , Kapur R. , Sengupta I. By VLSI Design 429-434 (2017)
Reservoir and mixer constrained scheduling for sample preparation on digital microfluidic biochips Agarwal V., Singla A. , Samiuddin M. , Roy S. , Ho T. , Sengupta I. , Bhattacharya B. By 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) 702-707 (2017)
Efficient implementation of adder circuits in memristive crossbar array Thangkhiew P. L., Gharpinde R. , Yadav D. N., Datta K. , Sengupta I. By IEEE Region 10 Conference (TENCON) 207-212 (2017)
Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip Manna K., Chattopadhyay S. , Sengupta I. By ISVLSI 583-586 (2016)
Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs Manna K., Sagar C. S., Chattopadhyay S. , Sengupta I. By ISVLSI 2016 529-534 (2016)
Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs Manna K., Sagar C. S., Chattopadhyay S. , Sengupta I. By ISVLSI 529-534 (2016)
Towards a cost metric for nearest neighbor constraints in reversible circuits Kole A., Datta K. , Sengupta I. , Wille R. By 7th Conference on Reversible Computation 273-278 (2015)
TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning Manna K., Teja V. S., Chattopadhyay S. , Sengupta I. By ISVLSI 392-397 (2015)
Windowing technique for Lazy Sorting of Encrypted data Chatterjee A., Sengupta I. By IEEE CNS - (2015)
GA based diagnostic test pattern generation for transition faults Bhar A., Chattopadhyay S. , Sengupta I. , Kapur R. By VDAT 1-6 (2015)
BDD-based synthesis for all-optical Mach-Zehnder interferometer circuits Schonborn E., Datta K. , Wille R. , Sengupta I. , Rahaman H. , Drechsler R. By 28th International Conference on VLSI Design (VLSID-2015) 435-440 (2015)
Design and implementation of rotation symmetric S-boxes with high nonlinearity and high DPA resilience. Mazumdar B., Mukhopadhyay D. , Sengupta I. By HOST 2013 - (2013)
Accelerating Sorting of Fully Homomorphic Encrypted Data Chatterjee A., Kaushal M. , Sengupta I. By Indocrypt - (2013)
FPGA implementation of extended reconfigurable Binary Edwards Curve based processor Chatterjee A., Sengupta I. By ICNC - (2012)
High-Speed Unified Elliptic Curve Cryptosystem on FPGAs Using Binary Huff Curves Chatterjee A., Sengupta I. By VDAT - (2012)
FPGA implementation of binary edwards curve usingternary representation Chatterjee A., Sengupta I. By GLSVLSI, ACM Great Lakes Symposium on VLSI - (2011)
A Rerouting Technique with Minimum Traffic Disruption for Dynamic Provisioning of Lightpaths Datta R., Ghose S. , Sengupta I. By IEEE International Conference on Networks - (2003)
Lightpath Provisioning in Wavelength Selective WDM Networks using GMPLS Datta R., Ghose S. , Sengupta I. By 6th International Conference on Information Technology - (2003)
Reformatting Test Patterns for Embedded Core Based Systems Using Test Access Mechanism (TAM) Switch Basu S., Mukhopadhyay D. , Chowdhury D. R., Sengupta I. , Bhawmick S. By Proceedings of International Conference on ASP-DAC and VLSI Design 2002 - (2002)

Educational Package

Ethical Hacking Sengupta I. By - (2019)
Embedded System Design Using ARM Datta K., Sengupta I. By - (2018)
Hardware Modeling using Verilog Sengupta I. By - (2018)

Edited Volume

Message from the ATS 2019 Organizing Co-Chairs Sengupta I., Chakrabarti A. By Proceedings of the Asian Test Symposium 2019-December xiii- (2019)

Symposium

Generalizing the concept of scalable reversible circuit synthesis for multiple-valued logic Zulehner A., Rani P. , Datta K. , Sengupta I. , Wille R. By IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL) 115-120 (2018)
Area efficient implementation of ripple carry adder using memristor crossbar arrays Thangkhiew P. L., Gharpinde R. , Paturi V. C., Datta K. , Sengupta I. By 11th International Design & Test Symposium (IDT-2016) 142-147 (2016)
TSV placement and core mapping for 3D mesh based network-on-chip design using extended Kernighan-Lin partitioning Manna K., Sri Teja V. S., Chattopadhyay S. , Sengupta I. By IEEE Computer Society Annual Symposium on VLSI (ISVLSI-2015) 392-397 (2015)
BDD based synthesis of Boolean functions using memristors. Chakraborti S., Paturi V. C., Datta K. , Sengupta I. By International Design & Test Symposium (IDT-2014) 136-141 (2014)

Workshop

New Scheme for Design of Static VirtualTopology in Wide Area Optical Networks Datta R., Ghose S. , Sengupta I. By International Workshop on Distributed Computing, 280-289 (2002)

Computer Science and Engineering

Faculty

Research Areas

Principal Investigator

Co-Principal Investigator

Ph. D. Students

Dev Narayan Yadav

Pravanjan Samanta