My research is focussed primarily in the area of designing various high speed parallel and pipelined VLSI architectures. Most of the works are related to the design and development of CORDIC based high throughput digital VLSI architectures for signal processing applications, ranging from those in the image processing, communication, to those in the biomedical domain. CORDIC provides an efficient and economic means of implementing transcendental functions in digital hardware that uses binary arithmetic. The developed architectures are mainly targeted to be deployed in real-time environments. One of the significant contributions is in the reduction of the latency of such pipelined structures. Though mostly the architectures designed are working in the digital domain, another significant research direction is towards the design of sampled analog architectures that can implement any digital signal processing algorithm much economically with unquantized samples using analog techniques, thereby having the best of both the analog and the digital worlds. This technique is capable of providing cost-effective solutions for the signal processing applications where a moderate accuracy of computation is sufficient. In a nutshell, my research area is mostly in the field of the design and development of high speed low latency VLSI architecture for real time signal processing applications.
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Novel Moving Coprime Array Configurations for Real-Valued Sources Patra R.K., Dhar A.S. By IEEE Signal Processing Letters 29 657-661 (2022)
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Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables Palchaudhuri A., Dhar A.S. By Journal of Electronic Testing: Theory and Applications (JETTA) 36 519-536 (2020)
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A special coprime array configuration for increased degrees of freedom Patra R.K., Dhar A.S. By Digital Signal Processing 122 103369- (2022)
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A new fraction phase based low energy frequency calibration architecture along with an ultra low power VCO design Ghosh A., Dhar A.S., Halder A. By Analog Integrated Circuits and Signal Processing 111 117-135 (2022)
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A Novel Nested Array for Real-Valued Sources Exploiting Array Motion Patra R.K., Dhar A.S. By IEEE Signal Processing Letters 28 1375-1379 (2021)
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Design automation for tree-based nearest neighborhood-aware placement of high-speed cellular automata on FPGA with scan path insertion Palchaudhuri A., Sharma S., Dhar A.S. By ACM Transactions on Design Automation of Electronic Systems 26 1-34 (2021)
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Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support Palchaudhuri A., Dhar A.S. By Journal of Parallel and Distributed Computing 151 13-23 (2021)
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A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation Banerjee A., Dhar A.S. By Circuits, Systems, and Signal Processing 40 311-334 (2021)
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SIBAM-sign inclusive broken array multiplier design for error tolerant applications Sinha Roy A., Dhar A.S. By IEEE Transactions on Circuits and Systems II: Express Briefs 67 2702-2706 (2020)
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On Fast and Exact Computation of Error Metrics in Approximate LSB Adders Sinha Roy A., Biswas R., Dhar A.S. By IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 876-889 (2020)
- Co-Principal Investigator
Ph. D. Students
Rajen Kumar Patra
Area of Research: VLSI SIgnal Processing
Sahadeb Santra
Area of Research: VLSI Architecture Design
